Coverage - SVA: The Power of Assertions in SystemVerilog - page 414

Example 18.11. Cover the time interval distribution between request req and
acknowledgment ack .
Solution:

checker req_ack_window2(
req, ack,
event clk = $inferred_clock,
untyped rst = $inferred_disable

);

default clocking @clk; endclocking
default disable iff rst;
int unsigned n=0;

always_ff @clk
if (rst || ack) n <= 0;
else if (req) n <= 1;
else if (n == 0) n <= 0;
else n<=n+1;

covergroup cg_win @(clk);
coverpoint n iff (ack && !rst);
endgroup : cg_win
cg_win cg = new ();
endchecker : req_ack_window2
Capture of the value of n in the covergroup happens when the clocking event
@clk takes place, i.e., before n is reset to 0 by nonblocking assignment.
We mentioned earlier that for efficiency reasons in FV, checker variables should
have the smallest possible size. In this example, n is defined as an unsigned int ,
which is of size 32 bits. One reason for this declaration is that we do not know
the maximal size of the time window, yet we need to reserve a large enough upper
bound. More importantly, the goal of this checker is to collect coverage information
in the covergroup in simulation, where int variables are efficient. The checker is
not intended for use in FV. t

In the following section, we examine effects of strong and weak properties in
cover property statements.

18.4 Coverage on Weak and Strong Properties

An important enhancement to SystemVerilog Assertions is the explicit notion of
property strength (see Chaps. 10 and 21 ). In simulation, the impact of strength
is seen on the result of property evaluation at the end of simulation, or more
specifically, when there is no further clock tick. In the case of cover property
statements, an evaluation attempt of a strong property for which there are not enough
clock ticks to reach a definitive decision yields the result not covered . This is unlike
in assert property statements, where such a situation leads to a failure of the
evaluation attempt.