Coverage - SVA: The Power of Assertions in SystemVerilog - page 413

There is no way to “generate” a set of bins in a loop; they must be enumerated.
To remedy this issue, a task can be created that decodes which bits are set in
covered , and then calls method sample for each such bit, passing its index. The task
is then called from the property in place of the sample method. The covergroup
must be modified so that the index into the vector is the coverpoint variable and it
has as many bins as the width of the vector. Both of these improvements are left as
an exercise at the end of the chapter.

18.3 Covergroups in Checkers

Checkers can be used to encapsulate coverage collection statements. Both assertion
cover statements and covergroup constructs are allowed in checkers. We show an
example of using cover statement in checkers in Example 24.4 . In this section, we
focus on covergroups.

Example 18.10. Check that all states of the FSM are visited. Let the FSM states be
described by the following enumeration:

typedef enum {
INIT,
IDLE,
SEND,
WAIT,
RECEIVE,
TO
} state_t;
The following checker collects coverage information about FSM states.

checker cover_fsm(
state_t state,
event clk = $inferred_clock,
untyped rst = $inferred_disable

);

covergroup cg_state @clk;
coverpoint state iff (!rst);
option.per_instance = 1;
endgroup : cg_state
cg_state cg = new ();
endchecker : cover_fsm
This checker contains a covergroup cg_state triggered by the clocking event
@clk . Coverage is collected in bins defined by the values of the enumeration type
state_t , but only when rst is low. Recall that for actual coverage collection to
take place, it is required to instantiate the covergroup using the new operator. t

It is possible to use checker variables in covergroups contained in the same
checker.