An Apology for Local Variables - SVA: The Power of Assertions in SystemVerilog - page 331

Chapter 15
An Apology for Local Variables
Local color has a fatal tendency to remain local; but it is also
true that the universal often borders on the void.
— DuBose Heyward and Hervey Allen
Local variables are a powerful feature of SystemVerilog Assertions that enable an
assertion to capture the value of an expression at a specified point in its evaluation
and store that value for later reference, perhaps after further modification. This
feature makes the encoding of many assertions much easier and helps to eliminate
the need for auxiliary state machines to support assertions.
A local variable must be declared within the declaration of a named sequence
or property, and the scope of a local variable does not extend outside the sequence
or property in which it is declared. Local variables are, therefore, not a first-class
construct of SVA. Each evaluation attempt of a named sequence or property has its
own copies of the local variables declared within it. In this sense, local variables are
“local” to these individual evaluation attempts.
This chapter gives an intuitive introduction to local variables based on examples.
For each example, an alternative encoding is shown that does not use local variables.
By comparing the encodings, the reader should gain an appreciation for the
semantics and, in most cases, the benefits of local variables. Throughout this chapter,
we assume that all assertions are clocked at posedge clk and that there is a default
clocking specification.
The examples described in this chapter can be implemented naturally as checkers.
However, in order to make the study of local variables independent of checkers,
we have rendered all the examples as modules or module fragments. Section 9.1
contains a detailed discussion of both module- and checker-based implementations
of the sequential protocol of Sect. 15.2 .Exercise 15.11 explores checker-based
implementation of the protocols of this chapter.