Procedural Concurrent Assertions - SVA: The Power of Assertions in SystemVerilog - page 330

B <= B_in;
chk chk_1(A, B);

end

2.

always @( posedge clk) begin
for ( int i=0; i<8; i++) begin
A[i] <= A_in[i];
chk chk_2(A[i], B);

end
B <= B_in;

end

3.

always @( posedge clk) begin
automatic logic T <= B_in;
A <= A_in;
chk chk_3(A, T);

end

4.

always @( posedge clk or negedge B_in) begin
A <= A_in;
B <= B_in;
chk chk_4(A, B);

end

5.

always @( posedge clk or negedge B_in) begin
A <= A_in;
B <= B_in;
chk chk_5(A, B, posedge clk or negedge B_in);

end

6.

always @( posedge clk or negedge rst_n) begin
A <= A_in;
B <= B_in;
chk chk_6(A, B);

end