Introduction - SVA: The Power of Assertions in SystemVerilog - page 2

Chapter 1
Introduction

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The beginning of all arts is difficult.

In comparison with the total chip development effort, the portion of effort spent in
design verification is growing at a faster rate and thus consuming a significantly
larger portion of the development cost. Despite more automation of various
processes and new techniques, the cost containment for verification continues to be
a challenge. There are at least two important cost motivations behind the increased
effort. One is the damaging effects of a late discovery of a bug in the design flow
on project schedules, which ultimately results in product delays. The other is the
enormous manufacturing cost of a chip re-spin due to revelation of a design flaw
after the initial prototype of the chip.
Consequently, there is a strong belief that investing more in developing new
design verification techniques and, correspondingly, increased effort to uncover
design bugs early in the design flow are worthwhile. We now have new techniques,
such as constrained random simulation, verification coverage closure, and assertion
checking, employed by many major organizations with the aim of speeding up
creation of testbenches and uncovering design errors.
SystemVerilog [ 8 ] is an extension of Verilog [ 2 ], 1 a well-known Hardware
Description Language (HDL), to support new verification techniques that have
already shown promising results in various organizations. Whereas Verilog was
oriented primarily to design and test at the Register Transfer Level (RTL) and
gate level, SystemVerilog added means for describing testbenches (SystemVerilog
Testbench, SVTB), defining functional coverage, and specifying assertions

1 Until 2009, Verilog and SystemVerilog had separate standards. In 2009 both standards were
merged into the SystemVerilog standard.