Introduction - SVA: The Power of Assertions in SystemVerilog - page 3

(SystemVerilog Assertions, SVA). 2 By virtue of many new enhancements geared
toward testing and checking, SystemVerilog surpassed Verilog as an HDL to become
an HDVL—Hardware Description and Verification Language.
The assertions technology was developed on the premise that writing specifi-
cations formally plays a critical role in detecting design errors. This is because
tools can automatically detect errors based on the implemented design and its
specification [ 49 ]. Keeping this goal in mind, SVA was designed as an integral part
of SystemVerilog. 3
This topic is dedicated to SystemVerilog Assertions. It teaches how to write
assertions, how to design and use assertion libraries, and it discusses assertion appli-
cations and checking. To read and to understand this topic, very basic knowledge of
SystemVerilog is sufficient. A tour of important features of SystemVerilog is pre-
sented in Chap. 2 . For an introduction to the basic Verilog layer of SystemVerilog,
see [ 61 ].
In this chapter, we introduce SystemVerilog assertions informally, before their
systematic treatment in the subsequent parts. For developing intuition on assertions,
their meaning is explained by way of simple examples. The reader does not have
to understand all the details at this stage, but only to grasp the concepts behind
the examples. This chapter also includes an informal introduction of SVA language
features that are handled in great detail in the rest of this topic.

1.1 The Concept of Assertion

An assertion is a positive statement about a property of a design. It is positive
in the sense that, should the statement be found as false, it indicates an error.
Designers place assertions to express the intended behavior as specifications that
can be interpreted and analyzed by tools. Since the property only states the behavior,
it is often used to ensure that the design implementation of the behavior matches the
assertion.
The use of assertions in contemporary hardware design methodologies has
become widespread and matured over the past years. In programming languages,
assertions have had a longer history of use, primarily because the assertions tend
to be simpler, embedded in the code to check Boolean properties. HDLs model
behavior over explicit time domains, with properties synchronous to clocks as well
as asynchronous with specific time delays. This aspect of HDL modeling pushed
forward the development of language techniques for expressing complex temporal
behavior in the form of assertions and algorithms to interpret temporal assertions.
As a result, several commercial languages have emerged to support the growing

2 SystemVerilog also introduced many important object-oriented enhancements to Verilog, such as
aggregate data types, classes, and interfaces [ 5 ].
3 The history of the SVA standardization is described in [ 25 ].