Digital Signal Processing Reference
In-Depth Information
=
5
V
R
1
2
1
2
VV
=
b
+
b
0
R
1
0
1
2
V
R
I
=
R
R
1
I
/2
R
R
0
b
1
=
1
2
R
R
R
V
0
−
1
I
/4
−
0
b
0
=
0
2
R
Phase shfter
Adder
I
/4
2
R
FIGURE 2.28
R-2R ladder DAC.
from all branches. The feedback resistor R in the adder provides overall amplification. The ladder
network is equivalent to two 2R resistors in parallel. The entire network has a total current of
I ¼
V
R
R
using Ohm's law, where
V
R
is the reference voltage, chosen to be 5 volts for our example.
Hence, half of the total current flows into the
b
1
branch, while the other half flows into the rest of the
network. The halving process repeats for each branch successively to the lower bit branches to get lower
bit weights. The second operational amplifier acts like a phase shifter to cancel the negative sign of the
adder output. Using the basic electric circuit principle, we can determine the DAC output voltage as
1
2
1
b
1
þ
2
2
b
0
1
V
0
¼ V
R
where
b
1
and
b
0
are bits in the 2-bit binary code, with
b
0
as the least significant bit (LSB).
1
2
1
1
þ
2
2
0
1
V
0
¼
5
¼
2
:
5 volts
As we can see, the recovered voltage of
V
0
¼
2
:
5 volts introduces voltage error as compared with
V
in
¼
3 volts, discussed in the ADC stage. This is due to the fact that in the flash ADC unit, we use
only four (i.e., finite) voltage levels to represent continuous (infinitely possible) analog voltage values.
This is called
quantization error
, obtained by subtracting the original analog voltage from the
recovered analog voltage. For our example, the quantization error is
V
0
V
in
¼
2
:
5
3
¼
0
:
5 volts
Next, we focus on quantization development. The process of converting analog voltage with infinite
precision to finite precision is called the
quantization process
. For example, if the digital processor has
only a 3-bit word, the amplitudes can be converted into eight different levels.
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