Digital Signal Processing Reference
In-Depth Information
x
()
ADC
Anti-
aliasing
filter
Digital
signal
processor
y
(
)
Quantization
binary
encoder
Sample
and hold
Zeroth-
order
hold
Anti-
image
filter
DAC
FIGURE 2.26
A block diagram for a DSP system.
In this chapter, we will focus on a simple 2-bit flash ADC unit, described in
Figure 2.27
, for illustrative
purposes. Sigma-delta ADC will be studied in Chapter 12.
As shown in
Figure 2.27
, the 2-bit flash ADC unit consists of a serial reference voltage created by
the equal value resistors, a set of comparators, and logic units. As an example, the reference voltages in
the figure are 1.25 volts, 2.5 volts, 3.75 volts, and 5 volts, respectively. If an analog sample-and-hold
voltage is
V
in
¼
3 volts, then the lower two comparators will each output logic 1. Through the logic
units, only the line labeled 10 is actively high, and the rest of lines are actively low. Hence, the
encoding logic circuit outputs a 2-bit binary code of 10.
Flash ADC offers the advantage of high conversion speed, since all bits are acquired at the same
time.
Figure 2.28
illustrates a simple 2-bit DAC unit using an R-2R ladder. The DAC contains the R-2R
ladder circuit, a set of single-throw switches, an adder, and a phase shifter. If a bit is logic 0, the switch
connects a 2R resistor to ground. If a bit is logic 1, the corresponding 2R resistor is connected to the
branch to the input of the operational amplifier (adder). When the operational amplifier operates in
a linear range, the negative input is virtually equal to the positive input. The adder adds all the currents
V
R
=
5
V
in
logic 0
Encoding
logic
R
11
Comparators
+
−
logic 1
3
4
V
R
10
=
375
.
10
logic 0
logic 1
R
logic 0
V
R
2
+
−
01
=
25
.
logic 1
logic 0
R
+
−
00
V
R
4
=
125
.
logic 0
logic 1
R
FIGURE 2.27
An example of a 2-bit flash ADC.
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