Hardware and Software for Digital Signal Processors - Digital Signal Processing: Fundamentals and Applications - page 429

the floating-point results. Eight auxiliary registers can be used for addressing and for integer arith-
metic. These registers provide internal temporary storage of internal variables instead of external
memory storage, to allow performance of arithmetic between registers. In this way, program efficiency
is greatly increased.
The prominent feature of C3x is its floating-point capability, allowing operation of numbers with
a very large dynamic range. It offers implementation of the DSP algorithm without worrying about
problems such as overflows and coefficient quantization. Three floating-point formats are supported. A
short 16-bit floating-point format has 4 exponent bits, 1 sign bit, and 11 mantissa bits. A 32-bit single
precision format has 8 exponent bits, 1 sign bit, and 23 fraction bits. A 40-bit extended precision
format contains 8 exponent bits, 1 sign bit, and 31 fraction bits. Although the formats are slightly
different from the IEEE 754 standard, conversions are available between these formats.
The TMS320C30 offers high-speed performance with 60-nanosecond single-cycle instruction
execution time, which is equivalent to 16.7 MIPS. For speech quality applications with an 8 kHz
sampling rate, it can handle over 2,000 single-cycle instructions between two samples (125 micro-
seconds). With instruction enhancements such as pipelines executing each instruction in a single cycle
(four cycles required from fetch to execution by the instruction itself) and a multiple interrupt
structure, this high-speed processor validates implementation of real-time applications in floating-
point arithmetic.

9.5 FINITE IMPULSE RESPONSE AND INFINITE IMPULSE RESPONSE
FILTER IMPLEMENTATIONS IN FIXED-POINT SYSTEMS
With knowledge of the IEEE format and of filter realization structures such as direct-form I, direct-
form II, and parallel and cascade forms (Chapter 6), we can study digital filter implementation in
the fixed-point processor. In the fixed-point system, where only integer arithmetic is used, we
prefer input data, filter coefficients, and processed output data to be in the Q-format. In this way,
we avoid overflow due to multiplication and can prevent overflow due to addition by scaling input
data. When the filter coefficients are out of the Q-format range, coefficient scaling must be taken
into account to maintain the Q-format. We develop FIR filter implementation in Q-format first, and
then infinite impulse response (IIR) filter implementation next. In addition, we assume that with
a given input range in Q-format, the filter output is always in Q-format even if the filter passband
gain is larger than 1.
First, to avoid the overflow for an adder, we can scale the input down by a scale factor S , which can
be safely determined by the following equation

N
k ¼ 0 jhðkÞj ¼ I max ,ðjhð 0 Þj þ jhð 1 Þj þ jhð 2 Þj þ/Þ

S ¼ I max , (9.2)

where hðkÞ is the impulse response of the adder output and I max the maximum amplitude of the input in
Q-format. Note that this is not an optimal factor in terms of reduced signal-to-noise ratio. However, it
shall prevent the overflow. Equation (9.2) means that the adder output can actually be expressed as
a convolution output:

adder output ¼ hð 0 ÞxðnÞþhð 1 Þxðn 1 Þþhð 2 Þxðn 2 Þþ/