Digital Signal Processing Reference
In-Depth Information
Program
cache
(64x32
RAM
block 0
(1Kx32)
RAM
block 1
(1Kx32)
ROM
block 0
(4Kx32)
XRDY
XRDY
IOSTRB
IOST
RB
/
XD
31− 0
A
12− 0
XR W
/
XD
31− 0
XA
12
− 0
MS
TRB
XR W
Data bus
X
MSTRB
RDY
DMA
Address generators
CPU
Serial
port 0
I
NT
3
0
−
Integer/
Floating-point
Multiplier
Integer/
Floating-point
ALU
8 Extended-precision
registers
Address
generator 0
IACK
XF
1
0
Control registers
Serial
port 1
−
MCBL MP
/
X
1
Timer 0
X CLKIN
2/
Address
generator 1
V
DD
V
SS
Timer 1
8 Auxilliary registers
12 Control registers
SHZ
FIGURE 9.14
The typical TMS320C3x floating-point DS processor.
(Texas Instruments 1991), the TMS320C6x CPU and Instruction Set Reference Guide (Texas
Instruments, 1998), and other studies (Dahnoun, 2000; Embree, 1995; Ifeachor and Jervis, 2002;
Kehtaranavaz and Simsek, 2000; Sorensen and Chen, 1997; Van der Vegte, 2002). The TMS320C3x
family consists of 32-bit single chip floating-point processors that support both integer and floating-
point operations.
The processor has a large memory space and is equipped with dual-access on-chip memories. A
program cache is employed to enhance the execution of commonly used codes. Similar to the fixed-
point processor, it uses the Harvard architecture, where there are separate buses used for program and
data so that instructions can be fetched at the same time that data are being accessed. There also exist
memory buses and data buses for direct-memory access (DMA) for concurrent I/O and CPU opera-
tions, and peripheral access such as serial ports, I/O ports, memory expansion, and an external clock.
The C3x CPU contains the floating-point/integer multiplier; an ALU, which is capable of operating
both integer and floating-point arithmetic; a 32-bit barrel shifter; internal buses; a CPU register file;
and dedicated auxiliary register arithmetic units (ARAUs). The multiplier operates single-cycle
multiplications on 24-bit integers and on 32-bit floating-point values. Using parallel instructions to
perform a multiplication, an ALU will cost a single cycle, which means that a multiplication and an
addition are equally fast. The ARAUs support addressing modes, in which some of them are specific to
DSP such as circular buffering and bit-reversal addressing (digital filtering and FFT operations). The
CPU register file offers 28 registers, which can be operated on by the multiplier and ALU. The special
functions of the registers include eight-extended 40-bit precision registers for maintaining accuracy of
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