Hardware Reference
In-Depth Information
Outputs (Y0 to Y7) are active low and thus are ideal for use as chip select or
enable signals. The truth table for the address decoder is as follows:
Address line
Base
Output
address
selected
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
(hex.)
(taken low)
0
0
0 11100000
0
0
0
0
0 11100001
4
1
0
0
0 11100010
8
2
0
0
0 11100011
C
3
0
0
0 11100100
0
4
0
0
0 11100101
4
5
0
0
0 11100110
8
6
0
0
0 11100111
C
7
0
0
1 xxxxxxxx n.a.
None
0
1
0 xxxxxxxx n.a.
None
0
1
1 xxxxxxxx n.a.
None
1
0
0 xxxxxxxx n.a.
None
1
0
1 xxxxxxxx n.a.
None
1
1
0 xxxxxxxx n.a.
None
1
1
1 xxxxxxxx n.a.
None
x
=
don't care; n.a. = not applicable.
The remaining address lines (Al and A0) provide four
address offsets
from
the base address, as follows:
Address lines
A1
A0
Offset value
0
0
0
0
1
1
1
0
2
1
1
3
As an example,
address 302 (hex.)
will be selected when the following
address pattern appears:
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
Al
A0
0
0
0 1110000010
Base address
=
300 H
Offset
=
2H
It is, of course, quite permissible to use the chip select lines without making
use of the register select lines, A1 and A0. In such cases, it is important to
remember that the I/O address will not be unique.
