Hardware Reference
In-Depth Information
Table 1.7
Bit functions in the 80286 machine status word
Bit
Name
Function
0
Protected mode (PE)
Enables protected mode and can only be
cleared by asserting the RESET signal.
1
Monitor processor (MP)
Allows WAIT instructions to cause a 'processor extension not present'
exception (Exception 7).
2
Emulate processor (EP)
Causes a 'processor extension not present' exception (Exception 7) on ESC
instructions to allow emulation of a processor extension.
3
Task switched (TS)
Indicates that the next instruction using a processor extension will cause
Exception 7 (allowing software to test whether the current processor
extension context belongs to the current task).
registers being initialized as shown in Table 1.6. The 80286 is packaged in a
68-pin JEDEC type-A plastic leadless chip carrier (PLCC), see Figure 1.12.
The 80386 (or '386) was designed as a
full
32-bit device capable of manipu-
lating data 32 bits at a time and communicating with the outside world through
a 32-bit address bus. The 80386 offers a 'virtual 8086' mode of operation
in which memory can be divided into 1 MB chunks with a different program
allocated to each partition.
The 80386 was available in two basic versions. The 80386SX operates intern-
ally as a 32-bit device but presents itself to the outside world through only 16 data
lines. This has made the CPU extremely popular for use in low-cost systems
which could still boast the processing power of a 386 (despite the obvious
limitation imposed by the reduced number of data lines, the 'SX' version of the
80386 runs at approximately 80% of the speed of its fully fledged counterpart).
The 80386 comprises a Bus Interface Unit (BIU), a Code Pre-fetch Unit,
an Instruction Decode Unit, an Execution Unit (EU), a Segmentation Unit,
and a Paging Unit. The Code Pre-fetch Unit performs the program 'look-
ahead' function. When the BIU is not performing bus cycles in the execution
of an instruction, the Code Pre-fetch Unit uses the BIU to fetch sequentially
the instruction stream. The pre-fetched instructions are stored in a 16-byte
'code queue' where they await processing by the Instruction Decode Unit.
The pre-fetch queue is fed to the Instruction Decode Unit which translates the
instructions into micro-code. These micro-coded instructions are then stored in
a three-deep instruction queue on a first-in first-out (FIFO) basis. This queue of
instructions awaits acceptance by the EU. Immediate data and op-code offsets
are also taken from the pre-fetch queue.
The 80486 processor was not merely an upgraded 80386 processor; its
redesigned architecture offers significantly faster processing speeds when run-
ning at the
same
clock speed as its predecessor. Enhancements include a built-in
maths coprocessor, internal cache memory, and cache memory control. The
internal cache is responsible for a significant increase in processing speed. As
a result, a '486 operating at 25 MHz can achieve a faster processing speed than
a '386 operating at 33 MHz.
The '486 uses a large number of additional signals associated with parity
checking (PCHK) and cache operation (AHOLD, FLUSH, etc.). The cache
comprises a set of four 2-KB blocks (128
16 bytes) of high-speed internal
