Hardware Reference
In-Depth Information
memory. Each 16-byte line of memory has a matching 21-bit 'tag'. This tag
comprises a 17-bit linear address together with four protection bits. The cache
control block contains 128 sets of 7 bits. Three of the bits are used to implement
the least recently used (LRU) system for replacement and the remaining 4 bits
are used to indicate valid data.
Interrupt handling
Interrupt service routines are subprograms stored away from the main body of
code that are available for execution whenever the relevant interrupt occurs.
However, since interrupts may occur at virtually any point in the execution of a
main program, the response must be automatic; the processor must suspend its
current task and save the return address so that the program can be resumed at the
point at which it was left. Note that the programmer must assume responsibility
for preserving the state of any registers which may have their contents altered
during execution of the interrupt service routine.
Figure 1.7 Internal architecture of the original Pentium processor
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