Encryption and Data Dependent Permutations: Implementation Cost and Performance Evaluation - Computer Network Security - page 345

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Fig. 5. Full Rolling (a) and Pipelined (b) Architecture

Table 3. Implementation Synthesis Results

FPGA Device (Xilinx Vitrex) ASIC (0.33 um)

Devices

F
(MHz)

Rate
(Gbps)

Area
sqmil

F
(MHz)

Rate
(Gbps)

Covered Area

Ciphers

FG CLB DFF

CIKS-1
(FR)

1723 907 192 81 0.648 3456 93 0.744

CIKS-1
(P)

14128 6346 576 81 5.184 21036 95 5.824

SPECTR
(FR)

1320 713 203 83 0.443 3194 91 0.485

SPECTR
(P)

10456 7021 832 83 5.312 32123 94 6.016

where: D Flip-Flops (DFF), Configurable Logic Blocks (CLB), Function Generators (FG),
Frequency (F) MHz.

4 VLSI Implementations Synthesis Results

The synthesis results are shown in Table 3, for CIKS-1 and SPECTR-H64, for both
hardware implementations (ASIC and FPGA).