Information Technology Reference
In-Depth Information
instruction parallelism level is a factor of great importance that must be taken under
consideration for microprocessor performance. Furthermore, the hardware devices of
these types can operate on arbitrary size of words, in contrast with processors, that
operate only on fixed-sized words.
ASICs are in general far more expensive devices due to time consuming and high
cost fabrication procedure, which is done by expertise industry departments. FPGAs
can be bought from anyone, since they are enough cheaper and can be programmed
or reconfigured by the designers/researchers. FPGAs have the major advantage that
can perform a completely different task/function after simple designers reconfigura-
tion. ASICs performance is tight and can not be modified after the chip's fabrication.
The offered reconfiguration has a speed penalty in these devices. ASICs have higher
speed performance in comparison with FPGAs. This is due to the fact that the recon-
figuration in FPGAs causes delays, introduced by the dedicated circuit's parts needed
to reconfiguration. In general, any implemented system of digital logic in an FPGA,
is slower than ASIC implementation of the same system.
Both CIKS-1 and SPECTR-H64 are examined in hardware implementation by us-
ing two different architectures: full rolling (FRA) and pipelined (PA) for both ASIC
and FPGA devices. The used full rolling architecture is shown in Figure 5,a. It is a
typical architecture for secret key block cipher implementation. The architecture
operates efficiently for both encryption and decryption process. According to this
architecture only one block of plaintext/ciphertext is transformed at a time. The nec-
essary number of clock cycles to encrypt/decrypt a data block is equal to the specified
number of cipher rounds (8 for CIKS-1 and 12 for SPECTR-H64). The key expan-
sion unit produces the appropriate round keys, which are stored and loaded in the
used RAM blocks. One round of the encryption algorithm is performed by the Data
Transformation Round Core. This core is a flexible combinational logic circuit and it
is supported by a
n
-bit register and
n
-bit multiplexer (64-bit for both CIKS-1 and
SPECTR-H64). In the first clock cycle, the
n
-bit plaintext/ciphertext is forced into the
data transformation round core. Then in each clock cycle, one round of the cipher is
performed and the transformed data are stored into the register. According to FRA a
64-bit data block is completely transformed every 8 clock cycles for CIKS-1 (8 trans-
formation rounds). The operation of SPECTR-H64 (12 transformation rounds) needs
12 clock cycles in order a 64-bit plaintext/ciphertext to be generated.
The second proposed architecture is a N-stages PA. In PA a RAM is used for the
round keys storage. Pipelining is not possible to be applied in many cryptographic
applications. However, CIKS-1 and SPECTR-H64 block ciphers structures provide
the availability to be implemented with pipelining technique. The pipelining architec-
ture offers the benefit of the high-speed performance. The implementation can be
applied in applications with hard throughput needs. This goal is achieved by using a
number of operating blocks with a final cost to the covered area. The proposed archi-
tecture uses 8 basic round blocks for CIKS-1 and 12 basic round blocks for SPECTR-
H64, which are cascaded by using equal number of pipelined registers. Based on this
design approach, 8 and 12 different 64-bit data blocks can be processed at the same
time, for CIKS-1 and SPECTR-H64 respectively. Pipelined proposed architecture
produces a new plaintext/ciphertext block every clock cycle.
