Information Technology Reference
In-Depth Information
V
(
l
) corresponding to the
l
th layer of the P
n/m
and to the (2
m
/
n
-
l
+1)th layer of the P
-
1
n/m
. For example, Fig. 1,d represents the CP-box operation P
-1
4/4
, which is the inverse
of the CP-box operation P
4/4
(Fig. 1,c). According to [3] the minimum number of
layers required to implement the CP box of the order
h
= 1, 2, 4, …,
n
/4 is
s
= log
2
n
+ log
2
h
= log
2
(
nh
). To implement the P
n/m
-box, where for
n =
2
k
, of the
maximum order one has to use (2log
2
n
- 1) layers.
2.1
DDP Architectures
In the next figures (Fig. 2-4) the architectures of the DDP boxes used in SPECTR-
H64 and CIKS-1 are illustrated. The basic building block of all these boxes is the P
2/1
box. For the hardware implementation of the P
2/1
two different approaches can be
followed: a 2-bit multiplexer and a logic gate chain. This box is designed with a chain
of logic gates, instead of a multiplexer block (Fig. 2). This selection has been done,
because the proposed logic-gate chain is faster compared with the 2-input multi-
plexer. The proposed P
2/1
box has time delay equal to 0.47 nsec and it is 21% less than
the time delay of the multiplexer design (0.6 nsec). In the following figures the archi-
tectures of different CP boxes are given. In addition, the architecture of the inverse
box of each CP box is also presented.
Fig. 2.
DDP Boxes: P
8/12
and P
-1
8/12
