Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 683

FIGURE C.50 An FP divide can cause a stall for an add that starts near the end of the
divide . The divide starts at cycle 0 and completes at cycle 35; the last 10 cycles of the divide
are shown. Since the divide makes heavy use of the rounding hardware needed by the add, it
stalls an add that starts in any of cycles 28 to 33. Notice that the add starting in cycle 28 will
be stalled until cycle 36. If the add started right after the divide, it would not conflict, since the
add could complete before the divide needed the shared stages, just as we saw in Figure
C.49 for a multiply and add. As in the earlier figure, this example assumes exactly one add
that reaches the U stage between clock cycles 26 and 35.
FIGURE C.51 A double-precision add is followed by a double-precision divide . If the di-
vide starts 1 cycle after the add, the divide stalls, but after that there is no conflict.
Performance Of The R4000 Pipeline
In this section, we examine the stalls that occur for the SPEC92 benchmarks when running on
the R4000 pipeline structure. There are four major causes of pipeline stalls or losses:
1. Load stalls —Delays arising from the use of a load result 1 or 2 cycles after the load