Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 663

but not those that precede that instruction. This prevents any state changes for instructions
that will not be completed before the exception is handled.
3. After the exception-handling routine in the operating system receives control, it immedi-
ately saves the PC of the faulting instruction. This value will be used to return from the
exception later.
When we use delayed branches, as mentioned in the last section, it is no longer possible to
re-create the state of the processor with a single PC because the instructions in the pipeline
may not be sequentially related. So we need to save and restore as many PCs as the length of
the branch delay plus one. This is done in the third step above.
After the exception has been handled, special instructions return the processor from the ex-
ception by reloading the PCs and restarting the instruction stream (using the instruction RFE
in MIPS). If the pipeline can be stopped so that the instructions just before the faulting in-
struction are completed and those after it can be restarted from scratch, the pipeline is said
to have precise exceptions . Ideally, the faulting instruction would not have changed the state,
and correctly handling some exceptions requires that the faulting instruction have no effects.
For other exceptions, such as floating-point exceptions, the faulting instruction on some pro-
cessors writes its result before the exception can be handled. In such cases, the hardware must
be prepared to retrieve the source operands, even if the destination is identical to one of the
source operands. Because floating-point operations may run for many cycles, it is highly likely
that some other instruction may have writen the source operands (as we will see in the next
section, floating-point operations often complete out of order). To overcome this, many recent
high-performance CPUs have introduced two modes of operation. One mode has precise ex-
ceptions and the other (fast or performance mode) does not. Of course, the precise exception
mode is slower, since it allows less overlap among floating-point instructions. In some high-
performance CPUs, including the Alpha 21064, Power2, and MIPS R8000, the precise mode is
often much slower (>10 times) and thus useful only for debugging of codes.
Supporting precise exceptions is a requirement in many systems, while in others it is “just”
valuable because it simplifies the operating system interface. At a minimum, any processor
with demand paging or IEEE arithmetic trap handlers must make its exceptions precise, either
in the hardware or with some software support. For integer pipelines, the task of creating pre-
cise exceptions is easier, and accommodating virtual memory strongly motivates the support
of precise exceptions for memory references. In practice, these reasons have led designers and
architects to always provide precise exceptions for the integer pipeline. In this section we led
scribe how to implement precise exceptions for the MIPS integer pipeline. We will describe
techniques for handling the more complex challenges arising in the floating-point pipeline in
Section C.5 .
Exceptions in MIPS
Figure C.32 shows the MIPS pipeline stages and which problem exceptions might occur in
each stage. With pipelining, multiple exceptions may occur in the same clock cycle because
there are multiple instructions in execution. For example, consider this instruction sequence: