Hardware Reference
In-Depth Information
FIGURE C.21
The implementation of the MIPS data path allows every instruction to be
executed in 4 or 5 clock cycles
. Although the PC is shown in the portion of the data path
that is used in instruction fetch and the registers are shown in the portion of the data path that
is used in instruction decode/register fetch, both of these functional units are read as well as
written by an instruction. Although we show these functional units in the cycle corresponding
to where they are read, the PC is written during the memory access clock cycle and the re-
gisters are written during the write-back clock cycle. In both cases, the writes in later pipe
stages are indicated by the multiplexer output (in memory access or write-back), which carries
a value back to the PC or registers. These backward-flowing signals introduce much of the
complexity of pipelining, since they indicate the possibility of hazards.
Although all processors today are pipelined, this multicycle implementation is a reasonable
approximation of how most processors would have been implemented in earlier times. A
simple finite-state machine could be used to implement the control following the 5-cycle struc-
ture shown above. For a much more complex processor, microcode control could be used. In
either event, an instruction sequence like that above would determine the structure of the con-
trol.
There are some hardware redundancies that could be eliminated in this multicycle imple-
mentation. For example, there are two ALUs: one to increment the PC and one used for ef-
fective address and ALU computation. Since they are not needed on the same clock cycle, we
could merge them by adding additional multiplexers and sharing the same ALU. Likewise,
instructions and data could be stored in the same memory, since the data and instruction ac-
cesses happen on different clock cycles.
Rather than optimize this simple implementation, we will leave the design as it is in
Figure
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