Hardware Reference
In-Depth Information
register A and on the value in register Imm. The result is placed in the temporary re-
gister ALUOutput.
■ Branch:
ALUOutput ← NPC + (Imm << 2);
Cond ← (A == 0)
Operation —The ALU adds the NPC to the sign-extended immediate value in Imm,
which is shifted left by 2 bits to create a word offset, to compute the address of the
branch target. Register A, which has been read in the prior cycle, is checked to determ-
ine whether the branch is taken. Since we are considering only one form of branch
( BEQZ ), the comparison is against 0. Note that BEQZ is actually a pseudoinstruction that
translates to a BEQ with R0 as an operand. For simplicity, this is the only form of branch
we consider.
The load-store architecture of MIPS means that effective address and execution cycles
can be combined into a single clock cycle, since no instruction needs to simultaneously
calculate a data address, calculate an instruction target address, and perform an oper-
ation on the data. The other integer instructions not included above are jumps of vari-
ous forms, which are similar to branches.
4. Memory access/branch completion cycle (MEM):
The PC is updated for all instructions: PC NPC;
■ Memory reference:
LMD ← Mem[ALUOutput] or
Mem[ALUOutput] ← B;
Operation —Access memory if needed. If instruction is a load, data return from
memory and are placed in the LMD (load memory data) register; if it is a store, then
the data from the B register are writen into memory. In either case, the address used
is the one computed during the prior cycle and stored in the register ALUOutput.
■ Branch:
if (cond) PC ← ALUOutput
Operation —If the instruction branches, the PC is replaced with the branch destination
address in the register ALUOutput.
5. Write-back cycle (WB):
■ Register-register ALU instruction:
Regs[rd] ← ALUOutput;
■ Register-immediate ALU instruction:
Regs[rt] ← ALUOutput;
■ Load instruction:
Regs[rt] ← LMD;
Operation —Write the result into the register file, whether it comes from the memory system
(which is in LMD) or from the ALU (which is in ALUOutput); the register destination field is
also in one of two positions (rd or rt) depending on the effective opcode.
Figure C.21 shows how an instruction flows through the data path. At the end of each clock
cycle, every value computed during that clock cycle and required on a later clock cycle (wheth-
er for this instruction or the next) is writen into a storage device, which may be memory,
a general-purpose register, the PC, or a temporary register (i.e., LMD, Imm, A, B, IR, NPC,
ALUOutput, or Cond). The temporary registers hold values between clock cycles for one
instruction, while the other storage elements are visible parts of the state and hold values
between successive instructions.
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