Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 634

FIGURE C.8 Forwarding of operand required by stores during MEM . The result of the
load is forwarded from the memory output to the memory input to be stored. In addition, the
ALU output is forwarded to the ALU input for the address calculation of both the load and the
store (this is no different than forwarding to another ALU operation). If the store depended on
an immediately preceding ALU operation (not shown above), the result would need to be for-
warded to prevent a stall.
Data Hazards Requiring Stalls
Unfortunately, not all potential data hazards can be handled by bypassing. Consider the fol-
lowing sequence of instructions:
LD R1,0(R2)
DSUB R4,R1,R5
AND R6,R1,R7
OR R8,R1,R9
The pipelined data path with the bypass paths for this example is shown in Figure C.9 . This
case is different from the situation with back-to-back ALU operations. The LD instruction does
not have the data until the end of clock cycle 4 (its MEM cycle), while the DSUB instruction needs
to have the data by the beginning of that clock cycle. Thus, the data hazard from using the
result of a load instruction cannot be completely eliminated with simple hardware. As Figure
C.9 shows, such a forwarding path would have to operate backward in time—a capability not
yet available to computer designers! We can forward the result immediately to the ALU from
the pipeline registers for use in the AND operation, which begins 2 clock cycles after the load.
Likewise, the OR instruction has no problem, since it receives the value through the register ile.
For the DSUB instruction, the forwarded result arrives too late—at the end of a clock cycle, when
it is needed at the beginning.