Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 633

FIGURE C.7 A set of instructions that depends on the DADD result uses forwarding paths
to avoid the data hazard . The inputs for the DSUB and AND instructions forward from the
pipeline registers to the first ALU input. The OR receives its result by forwarding through the re-
gister file, which is easily accomplished by reading the registers in the second half of the cycle
and writing in the first half, as the dashed lines on the registers indicate. Notice that the for-
warded result can go to either ALU input; in fact, both ALU inputs could use forwarded inputs
from either the same pipeline register or from different pipeline registers. This would occur, for
example, if the AND instruction was AND R6,R1,R4.
Forwarding can be generalized to include passing a result directly to the functional unit that
requires it: A result is forwarded from the pipeline register corresponding to the output of one
unit to the input of another, rather than just from the result of a unit to the input of the same
unit. Take, for example, the following sequence:
DADD R1,R2,R3
LD R4,0(R1)
SD R4,12(R1)
To prevent a stall in this sequence, we would need to forward the values of the ALU output
and memory unit output from the pipeline registers to the ALU and data memory inputs. Fig-
ure C.8 shows all the forwarding paths for this example.