Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 419

FIGURE 5.38 Cache and memory states in the multichip, multicore multiprocessor .
5.9 [10/10/10/10/15/15/15/15] <5.4> For each part of this exercise, assume the initial cache and
memory state in Figure 5.38 . Each part of this exercise specifies a sequence of one or more
CPU operations of the form:
P#: <op> <address> [ <-- <value> ]
where P# designates the CPU (e.g., P0,0 ), <op> is the CPU operation (e.g., read or write), <ad-
dress> denotes the memory address, and <value> indicates the new word to be assigned on a
write operation. What is the final state (i.e., coherence state, sharers/owners, tags, and data)
of the caches and memory after the given sequence of CPU operations has completed?
Also, what value is returned by each read operation?
a. [10] <5.4> P0,0: read 100
b. [10] <5.4> P0,0: read 128
c. [10] <5.4> P0,0: write 128 <-- 78
d. [10] <5.4> P0,0: read 120
e. [15] <5.4> P0,0: read 120
P1,0: read 120
f. [15] <5.4> P0,0: read 120
P1,0: write 120 <-- 80
g. [15] <5.4> P0,0: write 120 <-- 80
P1,0: read 120
h. [15] <5.4> P0,0: write 120 <-- 80
P1,0: write 120 <-- 90
5.10 [10/10/10/10] <5.4> Directory protocols are more scalable than snooping protocols be-
cause they send explicit request and invalidate messages to those nodes that have copies of
a block, while snooping protocols broadcast all requests and invalidates to all nodes. Con-
sider the eight-processor system illustrated in Figure 5.37 and assume that all caches not