Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 411

while to consider heterogeneous processors? Although no such multicore has yet been de-
livered and heterogeneous multiprocessors have had only limited success in special-purpose
computers or embedded systems, the possibilities are much broader in a multicore environ-
ment. As with many issues in multiprocessing, the answer will likely depend on the software
models and programming systems. If compilers and operating systems can effectively use het-
erogeneous processors, they will become more mainstream. At the present, dealing effectively
with modest numbers of homogeneous core strains is beyond existing compiler capability for
many applications, but multiprocessors that have heterogeneous cores with clear diferences
in functional capability and obvious methods to decompose an application are becoming more
commonplace, including special processing units such as GPUs and media processors. Em-
phasis on energy efficiency could also lead to cores with different performance to power ratios
being included.
In the 1995 edition of this text, we concluded the chapter with a discussion of two then-cur-
rent controversial issues:
1. What architecture would very large-scale, microprocessor-based multiprocessors use?
2. What was the role for multiprocessing in the future of microprocessor architecture?
The intervening years have largely resolved these two questions.
Because very large-scale multiprocessors did not become a major and growing market, the
only cost effective way to build such large-scale multiprocessors was to use clusters where the
individual nodes are either single multicore microprocessors or small-scale, shared-memory
multiprocessors (typically two to four multicores), and the interconnect technology is stand-
ard network technology. These clusters, which have been scaled to tens of thousands of pro-
cessors and installed in specially designed “warehouses,” are the subject of the next chapter.
The answer to the second question has become crystal clear in the last six or seven years:
The future performance growth in microprocessors will come from the exploitation of thread-
level parallelism through multicore processors rather than through exploiting more ILP.
As a consequence of this, cores have become the new building blocks of chips, and vendors
offer a variety of chips based around one core design using varying numbers of cores and L3
caches. For example, Figure 5.34 shows the Intel processor family built using the just the Ne-
halem core (used in the Xeon 7560 and i7)!