Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 360

in the right half of Figure 5.6 are combined with those in the left half of the figure to form a
single state diagram for each cache block.
To understand why this protocol works, observe that any valid cache block is either in the
shared state in one or more private caches or in the exclusive state in exactly one cache. Any
transition to the exclusive state (which is required for a processor to write to the block) re-
quires an invalidate or write miss to be placed on the bus, causing all local caches to make
the block invalid. In addition, if some other local cache had the block in exclusive state, that
local cache generates a write-back, which supplies the block containing the desired address.
Finally, if a read miss occurs on the bus to a block in the exclusive state, the local cache with
the exclusive copy changes its state to shared.
The actions in gray in Figure 5.7 , which handle read and write misses on the bus, are es-
sentially the snooping component of the protocol. One other property that is preserved in this
protocol, and in most other protocols, is that any memory block in the shared state is always
up to date in the outer shared cache (L2 or L3, or memory if there is no shared cache), which
simpliies the implementation. In fact, it does not mater whether the level out from the private
caches is a shared cache or memory; the key is that all accesses from the cores go through that
level.