Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 249

FIGURE 3.49 Sample code for register renaming practice .
FIGURE 3.50 Hint : Expected output of register renaming .
3.8 [20] <3.4> Exercise 3.7 explored simple register renaming: when the hardware register re-
namer sees a source register, it substitutes the destination T register of the last instruction
to have targeted that source register. When the rename table sees a destination register, it
substitutes the next available T for it, but superscalar designs need to handle multiple in-
structions per clock cycle at every stage in the machine, including the register renaming.
A simple scalar processor would therefore look up both src register mappings for each in-
struction and allocate a new dest mapping per clock cycle. Superscalar processors must be
able to do that as well, but they must also ensure that any dest -to- src relationships between
the two concurrent instructions are handled correctly. Consider the sample code sequence
in Figure 3.51 . Assume that we would like to simultaneously rename the first two instruc-
tions. Further assume that the next two available T registers to be used are known at the
beginning of the clock cycle in which these two instructions are being renamed. Conceptu-
ally, what we want is for the first instruction to do its rename table lookups and then up-
date the table per its destination's T register. Then the second instruction would do exactly
the same thing, and any interinstruction dependency would thereby be handled correctly.
But there's not enough time to write that T register designation into the renaming table and
then look it up again for the second instruction, all in the same clock cycle. That register
substitution must instead be done live (in parallel with the register rename table update).
Figure 3.52 shows a circuit diagram, using multiplexers and comparators, that will accom-
plish the necessary on-the-fly register renaming. Your task is to show the cycle-by-cycle
state of the rename table for every instruction of the code shown in Figure 3.51 . Assume
the table starts out with every entry equal to its index ( T0 = 0 ; T1 = 1 , …).