Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 171

The second advantage, the elimination of WAW and WAR hazards, is accomplished by re-
naming registers using the reservation stations and by the process of storing operands into the
reservation station as soon as they are available.
For example, the code sequence in Figure 3.7 issues both the DIV.D and the ADD.D , even though
there is a WAR hazard involving F6 . The hazard is eliminated in one of two ways. First, if the
instruction providing the value for the DIV.D has completed, then Vk will store the result, al-
lowing DIV.D to execute independent of the ADD.D (this is the case shown). On the other hand,if
if the L.D had not completed, then Qk would point to the Load1 reservation station, and the
DIV.D instruction would be independent of the ADD.D . Thus, in either case, the ADD.D can issue
and begin executing. Any uses of the result of the DIV.D would point to the reservation station,
allowing the ADD.D to complete and store its value into the registers without affecting the DIV.D .
We'll see an example of the elimination of a WAW hazard shortly. But let's first look at
how our earlier example continues execution. In this example, and the ones that follow in this
chapter, assume the following latencies: load is 1 clock cycle, add is 2 clock cycles, multiply is
6 clock cycles, and divide is 12 clock cycles.
Example
Using the same code segment as in the previous example (page 176), show what
the status tables look like when the MUL.D is ready to write its result.
Answer
The result is shown in the three tables in Figure 3.8 . Notice that ADD.D has com-
pleted since the operands of DIV.D were copied, thereby overcoming the WAR
hazard. Notice that even if the load of F6 was delayed, the add into F6 could be
executed without triggering a WAW hazard.