Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 170

FIGURE 3.7 Reservation stations and register tags shown when all of the
instructions have issued, but only the first load instruction has com-
pleted and written its result to the CDB . The second load has completed ef-
fective address calculation but is waiting on the memory unit. We use the array
Regs[ ] to refer to the register file and the array Mem[ ] to refer to the memory.
Remember that an operand is specified by either a Q field or a V field at any
time. Notice that the ADD.D instruction, which has a WAR hazard at the WB
stage, has issued and could complete before the DIV.D initiates.
Tomasulo's scheme offers two major advantages over earlier and simpler schemes: (1) the
distribution of the hazard detection logic, and (2) the elimination of stalls for WAW and WAR
hazards.
The first advantage arises from the distributed reservation stations and the use of the CDB.
If multiple instructions are waiting on a single result, and each instruction already has its oth-
er operand, then the instructions can be released simultaneously by the broadcast of the result
on the CDB. If a centralized register file were used, the units would have to read their results
from the registers when register buses are available.