Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 142

3
Instruction-Level Parallelism
and Its Exploitation
“Who's first?”
“America.”
“Who's second?”
“Sir, there is no second.”
Dialog between two observers of the sailing race later named “The America's Cup” and run every few years—the in-
spiration for John Cocke's naming of the IBM research processor as “America.” This processor was the precursor to the
RS/6000 series and the first superscalar microprocessor .
3.1 Instruction-Level Parallelism: Concepts and Challenges 148
3.2 Basic Compiler Techniques for Exposing ILP
3.3 Reducing Branch Costs with Advanced Branch Prediction
3.4 Overcoming Data Hazards with Dynamic Scheduling
3.5 Dynamic Scheduling: Examples and the Algorithm
3.6 Hardware-Based Speculation
3.7 Exploiting ILP Using Multiple Issue and Static Scheduling
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
3.9 Advanced Techniques for Instruction Delivery and Speculation
3.10 Studies of the Limitations of ILP
3.11 Cross-Cutting Issues: ILP Approaches and the Memory System
3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor
Throughput
3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-A8
3.14 Fallacies and Pitfalls