Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 141

lect statistics on overall performance and L1 data cache, L2, and L3 cache performance.
a. [20] <2.6> List the number of misses per 1K instruction of L1 data cache, L2, and L3 for
each dataset size and your processor model and speed. Based on the results, what can
you say about the L1 data cache, L2, and L3 cache sizes on your processor? Explain
your observations.
b. [20] <2.6> List the instructions per clock (IPC) for each dataset size and your processor
model and speed. Based on the results, what can you say about the L1, L2, and L3 miss
penalties on your processor? Explain your observations.
c. [20] <2.6> Run the program in VTune with input dataset size of 8 KB and 128 KB on
an Intel OOO processor. List the number of L1 data cache and L2 cache misses per 1K
instructions and the CPI for both configurations. What can you say about the efect-
iveness of memory latency hiding techniques in high-performance OOO processors?
Hint : You need to find the L1 data cache miss latency for your processor. For recent
Intel i7 processors, it is approximately 11 cycles.