Image Processing Reference
In-Depth Information
(
)
×
(
z
d
)
Fig. 29.
P
-Parallelisation of SISO subsystem
E
z
to
P
P
MIMO system
E
=
∈
[
−
]
P
SP
denotes the relative time offsets of connected pairs of
down- and up-samplers, respectively. Evidently, the
P
output signals of the SP interface
comprise all polyphase components of its input signal in a time-interleaved (SBSP) manner
at a
P
-fold lower sampling rate
f
d
=
P
PS
,and
p
0,
P
1
f
n
/
P
[Göckler & Groth (2004); Vaidyanathan (1993)].
Since the subsequent PS interface is inverse to the preceding SP interface [Göckler & Groth
(2004)], the SP-PS commutator cascade has unity transfer with zero delay in contrast to the
(
−
)
-fold delay of the BP Delay-Chain Perfect-Reconstruction system [Göckler & Groth
(2004); Vaidyanathan (1993)], as anticipated (cf. also Fig. 30).
After this preparation,
P
-fold parallelisation is readily achieved by shifting the (SISO)
subsystem
E
P
1
(
)
between the SP and PS interfaces by exploiting the noble identities
[Göckler & Groth (2004); Vaidyanathan (1993)] and some novel generalized SBSP multirate
identities [Groth (2003); Groth & Göckler (2001)]. Thus, as shown in Fig.
z
29(b), the two
interfaces are interconnected by an equivalent
P
×
P
MIMO system
E
(
z
d
)
, which represents
the
P
-fold parallelisation of
E
, where all operations of which are performed at the
P
-fold
reduced operational clock frequency
f
d
.
3.
Reconnect all parallelised subsystems
exactly in the same manner as in the original system.
This is always given, since parallelisation does not change the original numbers of input and
output ports of SISO or MIMO subsystems, respectively.
4.
Eliminate all interfractional cascade connections of PS-SP interfaces
using the obvious multirate
identity depicted in Fig. 30. Note that this elimination process requires identical up- and
down-sampling factors,
P
out,a
PS
(
z
)
P
in,b
SP
, of each PS-SP interface cascade restricting free choice
of
P
for subsystemparallelisation. As a result of parallelisation, all input signals of the original
(possibly MIMO) system are decomposed into
P
time-interleaved polyphase components by
a SP demultiplexer for subsequent parallel processing at a
P
-fold lower rate, and all system
output ports are provided with a PS commutator to interleave all low rate subsignals to form
the high speed output signals.
For illustration, we present the parallelisation of a unit delay
z
−
1
=
z
−
1/
d
,andofan
M
-fold
down-sampler with zero time offset [Groth (2003)], as shown in Fig. 31. The unit delay
(a) is realized by
P
parallel time-interleaved shimming delays to be implemented by suitable
system control:
:
=
0
,
where permutation is introduced for straightforward elimination of interfractional PS-SP
cascades according to Fig. 30 (
I
: Identity matrix). In case of down-sampling Fig. 31(b),
to increase efficiency, the
P
parallel down-samplers of the diagonal MIMO system
E
0
1
z
−
1/
P
d
E
P
×
P
(
z
d
)=
I
(
P
−
1
)
×
(
P
−
1
)
(
z
d
)
are
merged with the
P
down-samplers of the SP interface. Hence, by using suitable multirate
