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[Göckler & Groth (2004); Göckler & Eyssele (1992)] according to Subsection 3.2.1, or on the
COHBF approach investigated in Subsection 3.2.2. For both approaches it has been shown
that bandwidth-to-user assignment is feasible within reasonable constraints [Abdulazim et al.
(2007); Johansson & Löwenborg (2005); Kopmann et al. (2003)]: A minimum user channel
bandwidth, denoted by slot bandwidth
b
, can stepwise be extended by any integer number of
additional slots up to a desired maximum overall bandwidth that shall be assigned to a single
user.
However, as to challenge
i
), the above two FB approaches fundamentally differ from
each other: In a DFT PP FDMUX (
a
) the overall sample rate reduction is performed in
compliance with the number of user channels in a single step: all arithmetic operations are
carried out at the (lowest) output sampling rate [Vaidyanathan (1993)]. In contrast, in the
multistage FDMUX (
b
) the sampling rate is reduced stepwise, in each stage by a factor of two
[Göckler & Eyssele (1992)]. As a result, the polyphase approach (
a
) inherently represents a
completely parallelised structure, immediately usable for extremely high front-end sampling
frequencies, whereas the high-end stages of the tree-structured FDMUX (
b
) cannot be
implemented with standard space-proved CMOS technology. Hence, the tree structure,
FDMUX as well as FMUX, calls for a parallelisation of the high rate stages.
As motivated, this contribution deals with the parallelisation of multistage multirate systems.
To this end, we recall a general systematic procedure for multirate system parallelisation
[Groth (2003)], which is deployed in detail in Subsection 4.1. For proper understanding,
in Subsection 4.2 this procedure is applied to the high rate front-end stages of the FDMUX
part of the recently proposed tree-structured SBC-FDFMUX FB [Abdulazim & Göckler (2005);
Abdulazim et al. (2007)], which uniformly demultiplexes an FDM signal always down to slot
level (of bandwidth
b
) and that, after on-board switching, recombines these independent slot
signals to an FDM signal (FMUX) with different channel allocation -
FDFMUX functionality
.
If a single user occupies a multiple slot channel, the corresponding parts of FDMUX and
FMUX are matched for (nearly) perfect reconstruction of this wideband channel signal -
SBC
functionality
[Vaidyanathan (1993)]. Finally, some conclusions are drawn.
4.1 Sample-by-sample approach to parallelisation
In this subsection, we introduce the novel sample-by-sample processing (SBSP) approach to
parallelisation of digital multirate systems, as proposed by [Groth (2003)] where, without
any additional delay, all incoming signal samples are directly fed into assigned units for
immediate signal processing. Hence, in contrast to the widely used block processing (BP)
approach, SBSP does not increase latency.
In order to systematically parallelise a (multirate) system, we distinguish four procedural
steps [Groth (2003)]:
1.
Partition the original system
in (elementary SISO or MIMO) subsystems
E
(
)
with single or
multiple input and/or output ports, respectively, still operating at the original high clock
frequency
f
n
z
=
1/
T
that are simply amenable to parallelisation. To enumerate some of
these: Delay, multiplier, down- and up-sampler, summation and branching, but also suitable
compound subsystems such as SISO filters and FFT transform blocks.
2.
Parallelise each subsystem E
(
)
z
in an SBSP manner according to the desired individual degree
∈
N
of parallelisation
P
,where
P
. To this end, each subsystem is cascaded with a
P
-fold
SBSP serial-to-parallel (SP) commutator for signal decomposition (demultiplexing) followed
by a consistently connected
P
-fold parallel-to-serial (PS) commutator for recomposition
(remultiplexing) of the original signal, as depicted in Fig.
=
29(a). Here, obviously
P