Image Processing Reference
In-Depth Information
with
F
(1)
=
F
MSF
;
F
(2)
=
F
RSF
, and
F
(3)
=
F
RASF
,
F
(4)
=
F
RASF
,
respectively.
Any other feasible adjustments of the DEDR degrees of freedom (the regularization
parameters , , and the weight matrix
A
) provide other possible DEDR-related SSP
reconstruction techniques, that we do not consider in this study.
3. VLSI architecture based on Massively Parallel Processor Arrays
In this section, we present the design methodology for real time implementation of
specialized arrays of processors in VLSI architectures based on massively parallel processor
arrays (MPPAs) as coprocessors units that are integrated with a FPGA platform via the
HW/SW co-design paradigm. This approach represents a real possibility for low-power
high-speed reconstructive signal processing (SP) for the enhancement/reconstruction of RS
imagery. In addition, the authors believe that FPGA-based reconfigurable systems in
aggregation with custom VLSI architectures are emerging as newer solutions which offer
enormous computation potential in RS systems.
A brief perspective on the state-of-the-art of high-performance computing (HPC) techniques
in the context of remote sensing problems is provided. The wide range of computer
architectures (including homogeneous and heterogeneous clusters and groups of clusters,
large-scale distributed platforms and grid computing environments, specialized
architectures based on reconfigurable computing, and commodity graphic hardware) and
data processing techniques exemplifies a subject area that has drawn at the cutting edge of
science and technology. The utilization of parallel and distributed computing paradigms
anticipates ground-breaking perspectives for the exploitation of high-dimensional data
processing sets in many RS applications. Parallel computing architectures made up of
homogeneous and heterogeneous commodity computing resources have gained popularity
in the last few years due to the chance of building a high-performance system at a
reasonable cost. The scalability, code reusability, and load balance achieved by the proposed
implementation in such low-cost systems offer an unprecedented opportunity to explore
methodologies in other fields (e.g. data mining) that previously looked to be too
computationally intensive for practical applications due to the immense files common to
remote sensing problems (Plaza & Chang, 2008).
To address the required near-real-time computational mode by many RS applications, we
propose a high-speed low-power VLSI co-processor architecture based on MPPAs that is
aggregated with a FPGA via the HW/SW co-design paradigm. Experimental results
demonstrate that the hardware VLSI-FPGA platform of the presented DEDR algorithms
makes appropriate use of resources in the FPGA and provides a response in near-real-time
that is acceptable for newer RS applications.
3.1 Design flow
The all-software execution of the prescribed RS image formation and reconstructive signal
processing (SP) operations in modern high-speed personal computers (PC) or any digital
signal processors (DSP) platform may be intensively time consuming. These high
computational complexities of the general-form DEDR-POCS algorithms make them
definitely unacceptable for real time PC-aided implementation.
In this section, we describe a specific design flow of the proposed VLSI-FPGA architecture
for the implementation of the DEDR method via the HW/SW co-design paradigm. The
