Image Processing Reference
In-Depth Information
HW/SW co-design is a hybrid method aimed at increasing the flexibility of the
implementation and improvement of the overall design process (Castillo Atoche et al.,
2010a). When a co-processor-based solution is employed in the HW/SW co-design
architecture, the computational time can be drastically reduced. Two opposite alternatives
can be considered when exploring the HW/SW co-design of a complex SP system. One of
them is the use of standard components whose functionality can be defined by means of
programming. The other one is the implementation of this functionality via a
microelectronic circuit specifically tailored for that application. It is well known that the first
alternative (the software alternative) provides solutions that present a great flexibility in
spite of high area requirements and long execution times, while the second one (the
hardware alternative) optimizes the size aspects and the operation speed but limits the
flexibility of the solution. Halfway between both, hardware/software co-design techniques
try to obtain an appropriate trade-off between the advantages and drawbacks of these two
approaches.
In (Castillo Atoche et al., 2010a), an initial version of the HW/SW- architecture was
presented for implementing the digital processing of a large-scale RS imagery in the
operational context. The architecture developed in (Castillo Atoche et al., 2010a) did not
involve MPPAs and is considered here as a simply reference for the new pursued
HW/SW co-design paradigm, where the corresponding blocks are to be designed to
speed-up the digital SP operations of the DEDR-POCS-related algorithms developed at
the previous SW stage of the overall HW/SW co-design to meet the real time imaging
system requirements.
The proposed co-design flow encompasses the following general stages:
i. Algorithmic implementation (reference simulation in MATLAB and C++ platforms);
ii. Partitioning process of the computational tasks;
iii. Aggregation of parallel computing techniques;
iv. Architecture design procedure of the addressed reconstructive SP computational tasks
onto HW blocks (MPPAs);
3.1.1 Algorithmic implementation
In this sub-section, the procedures for computational implementation of the DEDR-related
robust space filter (RSF) and robust adaptive space filter (RASF) algorithms in the MATLAB
and C++ platforms are developed. This reference implementation scheme will be next
compared with the proposed architecture based on the use of a VLSI-FPGA platform.
Having established the optimal RSF/RASF estimator (20) and (21), let us now consider the
way in which the processing of the data vector u that results in the optimum estimate b
can be computationally performed. For this purpose, we refer to the estimator (20) as a
multi-stage computational procedure. We part the overall computations prescribed by the
estimator (16) into four following steps.
a. First Step: Data Innovations
At this stage the a priori known value of the data mean  
uSm is subtracted from the
b
uuS contains all new information regarding
the unknown deviations b = ( b - m b ) of the vector b from its prescribed (known) mean
value m b .
b.
data vector u . The innovations vector

b
Second Step: Rough Signal Estimation
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