EQUALIZATION - Advanced Signal Integrity for High-Speed Digital Design - page 521

Example 12-3 Transmit DLE Operation To further develop our understanding,
we step through operation of the discrete linear equalizer shown in Figure 12-26
for the case in which it is presented with a lone pulse input of 600 mV amplitude
and 1 ns width. For this example we use a tap delay T of 1 ns and the following
values for the tap weights: C − 1 =− 1 / 12, C 0 = 2/3, C 1 =− 1/6, and C 2 = 1/12.

1. The pulse arrives at the input to the filter, where it is multiplied by C − 1 ,
generating a precursor pulse of 50 mV amplitude and 1 ns duration.

2. After a delay of 1 ns, the pulse appears at the second tap and is multiplied
by C 0 , generating a 400-mV 1-ns cursor pulse.
3. One nanosecond later, the pulse is at the third tap, where it is weighted
with C 1 , generating the first postcursor pulse of

−

− 100 mV amplitude and

1 ns duration.
4. After an additional 1-ns delay, the input comes to the final tap, where
it undergoes multiplication with C 2 , creating a + 50-mV, 1-ns postcursor

pulse.

The summing element operates during the entire sequence. Since our input is
a lone pulse, the signal inputs to the filter taps on either side of our pulse do
not generate any “echoes,” so that the output from the equalizer is a linearly
weighted time-delayed version of the original input, as Figure 12-26b shows.

Equalization at the transmitter is often called transmitter preemphasis to reflect
the effect of the filter operation. As we have discussed, the function of the
equalizer is to provide a high-pass filtering effect to the signal. In a digital
signal, the highest-frequency content is contained in rapid transitions between
logic states, while low-frequency content is contained in portions of the signal
that do not make transitions. The manifestation in a discrete linear equalizer is
increased amplitude for the first bit after a logic transition relative to successive
bits. This effect is shown in Figure 12-27 for a 500-mV transmitter with 20%
equalization:

v max.swing − v min.swing

v total swing

500 mV 300 mV

500 mV

−

× 100 = × 100

= 20% =− 13 . 97 dB

The full signal swing occurs for the case when the signal transitions between logic
states for at least two successive bit positions. It ranges from 100 mV on the

low side to 400 mV on the high side, for a total of 500 mV. To find the minimum
swing we look at the waveform regions that contain multiple consecutive zeros
(0 mV) and 1's (300 mV). The variation in swing from 500 mV maximum to
300 mV minimum corresponds to 20% equalization.
High-speed signaling systems typically use as much drive current as possible in
order to maximize speed, the limitation being the maximum voltage swing that

−