I/O CIRCUITS AND MODELS - Advanced Signal Integrity for High-Speed Digital Design - page 483

P 1 P 2 P 3

v in

v out

N 1 N 2 N 3

Figure 11-39 Multistage controlled-rise-time transmitter.

requires multiple sets of v - t and i - v curves to properly model the behavior of
the circuit. IBIS provides a keyword to allow scheduling of the application of
the multiple curves to reflect the staged switching behavior.
IBIS supports up to 1000 v - t points per table, and the time step used in the
table should be minimized to provide maximum resolution. The test load that is
used in generating the v - t tables must be described in the model. The signal
integrity simulation tool will use this information from the model to reconcile
the output waveform to reflect the behavior when driving the actual system load.
As with the i - v curves, IBIS accommodates separate v - t curves for minimum,
typical, and maximum cases.

I/O Capacitance The capacitance of the I/O circuit includes the transistors,
on-die interconnect, and die pad, and can have separate values for minimum,
typical, and maximum cases. Designers have multiple options at their disposal
for extracting the I/O capacitance values. We describe one of them here. We
connect the circuit to an ac voltage source at the I/O pad so that we capture all
the contributors to the capacitance, as shown in Figure 11-40. By measuring the
current flow into the circuit, we can calculate the capacitance using

= −

Im (i ac )
2 πf v ac

C comp (11-12)

where f is the frequency of the ac source, v ac is the amplitude of the source,
and Im( i ac ) is the imaginary portion of the current flowing into the ac source.
If the I/O capacitance may be affected by the bias (dc) voltage of the circuit, we
must include a dc offset in the ac source. In addition, I/O capacitance typically
varies with frequency and applied voltage, so performing multiple extractions
while sweeping both of those parameters is recommended. For a given model,
simply choose the capacitance value that corresponds to expected switching
frequency and bias voltage of the application [IBIS, 2005].