TOPICS IN HIGH-SPEED CHANNEL MODELING - Advanced Signal Integrity for High-Speed Digital Design - page 431

Via pad

i

Port 1

Signal layer 1
Reference layer 2

− i

Reference layer 3
Signal layer 4

Stub
length

Port 2 Signal via Ground via

Signal layer 5
Reference layer 6

Reference layer 7
Signal layer 8

Back drilled
portion

Figure 10-17 Cross section a a backdrilled PTH via with a stub showing the nonideal
current return path through the ground via.

is included to provide a low-impedance path for the return current. Standard PTH
vias are constructed by drilling a hole in the board and plating the walls with
metal. A consequence of this manufacturing process is a “stub” that hangs off
the via for all cases except when the signal transitions thorough the entire board
(layers 1 to 8 in Figure 10-17). As will be shown later, the via stub has negative
effects on the signal integrity. A common design practice is to shorten the length
of the stub with precision depth backdrilling, as also depicted in Figure 10-17.
If a current i is driven into port 1 in Figure 10-17, it will propagate down
the transmission line on signal layer 1, pass through the via down to signal layer
4, and terminate at port 2. The return current i will be mirrored on reference

plane 2. Since the nearest return path from port 1 to port 2 is through the ground
via, the return current must diverge away from the ideal path. The magnitude
of the via inductance is therefore a function of the length of the via transition
from signal layer 1 to signal layer 2 and the distance between the signal via and
the ground via. The capacitance of the via will be dependent on the area of the
via pads, the distance between the via pads and the closest reference layer, the
capacitance of the via barrel to the adjacent planes it is passing through, and
the capacitance of the stub. These observations make it possible to deduce two
different forms of an equivalent circuit.
Figure 10-18a shows the equivalent circuit of a via for the case where the
stub length is zero and reference layers 2 and 3 are very far apart. In this sce-
nario, which is almost always the case with standard four-layer PCBs, the via
capacitance is dominated by the pads, so a very simple pi model can be used.
Figure 10-18b shows an equivalent circuit where reference layers 2 and 3 are
close in proximity and a stub may or may not exist. In this case, the barrel and
stub capacitances are no longer negligible and are simply combined with the pad

−