Graphics Programs Reference
In-Depth Information
Table 6.1: Specification of the transitions of the SPN of Fig. 6.1
transition
rate
semantics
T req1
λ 1
single-server
T req2
λ 2
single-server
T str1
α 1
single-server
T str2
α 2
single-server
T end1
µ 1
single-server
T end2
µ 2
single-server
Table 6.2: Initial marking of the SPN of Fig. 6.1
place
initial marking
p act1
1
p act2
1
p idle
1
be described by the evolution of the net.
A conflict exists in the behaviour of this system when both processors want
to simultaneously access the common memory, i.e., when transitions T str1
and T str2 are both enabled. According to equation ( 6.1) , in this situation,
transition T str1 fires with probability:
α 1
α 1 + α 2
P { T str1 } =
(6.13)
whereas transition T str2 fires with probability:
α 2
α 1 + α 2
P { T str2 } =
(6.14)
Notice that when the two transitions T str1 and T str2 are both enabled in a
given marking M, the speed at which the PN model exits from that marking
is the sum of the individual speeds of the two transitions and the conflict is
actually resolved only at the moment the first of them fires.
The reachability set of the SPN system of Fig. 6.1 is depicted in Table
6.3. The reachability graph is shown in Fig. 6.2, while the corresponding
CTMC state transition rate diagram is presented in Fig. 6.3. Finally, the
infinitesimal generator is reported in Fig. 6.4.
Assuming λ 1 = 1, λ 2 = 2, α 1 = α 2 = 100, µ 1 = 10, and µ 2 = 5, we can
write the system of linear equations whose solution yields the steady-state
distribution over the CTMC states:
 
 
 
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