The Rendering Pipeline - Practical Rendering and Computation with Direct3D 11 - page 185

Figure 3.39. Multiple vertex structures using the same output registers.

the output registers that are used to receive the output vertex data will overlap with one
another. This is depicted in Figure 3.39.
Since the output frequencies of the streams are not required to be equal, there is no
easy way to ensure that dynamic branching won't produce an execution path that streams
out the largest vertex for all vertex outputs. Therefore, the easiest way to ensure that only
1024 scalars are output is to determine at compile time the "worst case" vertex output and
only allow a valid number of those vertices to be streamed. Any other vertices that are
streamed out will only reduce the total number of scalars produced, ensuring that the limit
of 1024 scalars is observed.

Primitive Manipulations
Another interesting result of the geometry shader's process flow is that while primitives
must be passed into the stage, they may or may not be passed to the next stage. This lets the
geometry shader selectively discard unneeded geometry, reducing the amount of geometry
for the rasterizer to process, and allowing for special rendering operations that require only
a subset of a model to be rendered. A good example of this is the rendering of a model's
silhouette to indicate that it is highlighted.

Shadow Volumes

Shadow volumes are a shadowing technique that extracts a model's silhouette as viewed
from a light source. The extracted silhouette is expanded outward away from the light,
and this expanded geometry is rasterized into the stencil buffer 2 1 as an indication of which

pixels are inside of a shadow volume. This is the heart of the algorithm—the extracted
silhouette geometry forms a volume. If the viewer only sees one side of the shadow vol-
ume at a particular pixel, it means that that particular point in the scene is inside of
the shadow and would not be illuminated by the light. If the viewer can see both sides

2 1
The stencil buffer and its operation are described later in this chapter, in the output merger stage section.