Image Processing Reference
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new technology. The logic of using the majority gate, and the uniformity of wires
and processing elements, modify the way of thinking in designing circuits. For ex-
ample, the majority gate could simplify many nonlinear filters since it is, by itself,
a binary three point median.
In the rest of this section, the image processing morphological operations of ero-
sion and dilation, described in Sect. 4.2, will be implemented by using QCA tech-
nology, applying the methodology described in Sect. 4.4 and utilizing the simple
QCA circuit components presented in Sect. 4.3.
For the hardware implementation let us assume that black pixels correspond to
logic “1” and that white pixels correspond to logic “0”. It is also assumed that the
inputs are binary images with white background and black objects and that the struc-
turing element is a 3
3 pixels cross with origin its centric pixel, as they are pre-
sented in Fig. 4.1 or 4.2. Following the rules presented in methodology in the designs
that follow, the wire lengths are less than 10 cells, the length of phase blocks are 2
cells or more and the areas of clocking zones and uncovered areas have been kept
as small as possible.
×
4.5.1
QCA Implementation of Morphological Erosion
In the following, the QCA implementation of morphological erosion operation will
be described. By using the cross 3
3 pixels structuring element, the procedure that
applies the erosion can be simplified to the following steps. First, superimpose the
structuring element over every 3
×
×
3 region of the image. Then, if all the black pixels
of the structuring element coincide with black pixels on the input image, paint black
the pixel of the output image that corresponds to the structuring element origin. In
other cases the pixels of the output image are left white.
This operation can be designed in hardware by implementing a 5-input AND gate
as shown in Fig. 4.9, applying as inputs (i1 to i5) the values of the five input image
pixels that coincides to the five structuring element black pixels. In this figure the
“-1” denotes the polarization of the fixed cell that corresponds to logic “0”.
As it was presented in the previous section, a 2-input AND gate in QCA is real-
ized by clamping one input of the 3-input majority gate to logic “0”. The realization
of the 5-input AND gate is made by the proper connection of four 2-input AND
gates. In the design the maximum wire length in a clocking zone is kept to 5 cells
and the minimum distance between to wires is 2 cells.
The output of the 5-input AND gate will be logic “1” only if all the inputs are set
to logic “1” and the state of the output cell will define the value of the pixel of the
output image with coordinates that corresponds to the coordinates of the structuring
element origin pixel. So, if all the pixels of the input image (which coincides with
the structuring element) are black, then the pixel of the origin on the output image
will be black. In other cases, the output will be logic “0”, so the output pixel will be
white.
This QCA design was simulated and tested with the use of the QCADesigner
tool. According to this tool, the design consists of 35 cells covering an area of
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