Image Processing Reference
In-Depth Information
odd-line and even-line pixels are added into 250 lines from 500 lines. The combination pair
of adding is alternately changed between upper and lower adjacent pixels in each field.
Therefore, both the integration period and output period are 1/60 s long without time
overlapping between consecutive fields; no system lag occurs.
The above field integration mode is easily applied for monochrome images. But for the
case of a single-chip color camera (SCCC) system, which is the widest application, the key
is the color filter array solution, which makes it possible to produce a color image by com-
bination with field integration mode. After the key solution of color filter array and system
named line sequential color difference system
7
was proposed, the combination of the color
filter array and field integration mode became the standard technology of consumer-use
SCCCs such as camcorders.
5.1.2 Pixel Technology of IT-CCD
Signal charges are integrated at PDs at first, then read out to the VCCD channel, and trans-
ferred through the VCCD and HCCD channel to the output amplifier. As was already
mentioned, the most important feature of CCDs is low-noise performance by the grace of
complete charge transfer, as shown Figure 5.13a. But if larger level noises are generated in
a PD, low-noise performance at the next charge transfer process is not utilized. Therefore,
to make effective use of low-noise performance at the transfer stage, a high SNR at the PD
stage is indispensable, as shown in Figure 5.13b. As a result, developments to improve SNR
performance at pixel level by increasing signal charge quantity
S
and decreasing noise
electrons
N
are the history of CCD technology.
A cross-sectional structure of that kind of representative pixel technology is shown
in Figure 5.14. A silicon substrate of
n
-type, on which a
p
-well is formed, with a buried-
channel VCCD and pinned PD covered with a
p
+
layer, is arranged. The
n
-region of the PD
has low impurity concentration so that it is completely depleted after the signal charges are
read out to the VCCD channel. The
p
-well region just under the PD has a vertical overflow
drain (VOD) structure to drain excess carriers to the
n
-substrate before they spill over into
the VCCD channel or peripheral PDs, as mentioned in Section 5.1.1.2. In the upper region
(a)
Complete charge transfer
Complete transfer
All process flows are
sequential complete transfer
from one capacitor to the next
Low-noise and high-output voltage
High SNR
Noise electron number : 2-5e
(b)
→
→
→
output amplifier
PD
VCCD
HCCD
Low-noise performance through transfer process
Necessity of high SNR at PD phase
FIGURE 5.13
Features IT-CCDs: (a) low noise by complete charge transfer; (b) necessity of high signal and low-noise-level
pixel.
