Image Processing Reference
In-Depth Information
The operation is explained using Figure 2.27b. As for the input, reset level* just after the
reset operation of FD and signal level just after the signal charge transfer to FD appear
serially in alternate shifts. The signal component that is required is the difference between
the reset level and the following signal level of each input signal.
To that end, clamp pulse ϕ
CL
is applied to the clamp transistor in the reset level period
to set the clamp transistor to on-state. This connects node A with clamp voltage
V
clamp
.
Clamp operation is completed when the clamp transistor is switched to off-state and node
A is set to fixed clamp voltage
V
clamp
. Thus, each potential corresponding to reset level is
forced to set clamp voltage
V
clamp
independent of the original reset level in CDS operation.
After that, signal charges are transferred to FD, and signal level is output from SFA to
CDS input. Only the amount of change (signal component in the figure) of input signal
passes through the AC-coupling capacitor
C
C
to node A to change its potential from
V
clamp
to [
V
clamp
− signal component].
Then, sampling pulse ϕ
SH
is applied to the gate of the sampling transistor to set it on-
state. The potential [
V
clamp
− signal component] is held at the sampling capacitor
C
SH
and
kept till the next signal sampling by setting the sampling transistor off-state. Thus, the
CDS circuit can obtain a true signal component by removing the correlated noise involved
in both levels with the clamp operation of the reset level and the sampling operation of
the signal level. When the sampling operation is achieved at the sampling capacitor
C
SH
,
enough electric power is supplied by the SFA.
References
1. W. F. Kosonocky, J. E. Carnes, Basic concept of charge-coupled devices,
RCA Review
, 38, 566-
593, 1975.
2. N. Koike, I. Takemoto, K. Sato, A. Sasano, S. Nagahara, M. Kubo, Characteristics of an
npn
structure MOS imager for color camera,
Journal of the Institute of Television Engineers of Japan
,
33(7), 548-553, 1978.
3. W. F. Kosonocky, J. G. Carne, Charge-coupled digital circuit, in
Proceedings of the IEEE
International Solid-State Circuits Conference, Digest of Technical Papers
, pp. 162-163, February,
1971.
4. M. White, D. Lampe, F. Blaha, I. Mack, Characterization of surface channel CCD image arrays
at low light levels,
IEEE Journal of Solid-State Circuits
, 9(1), 1-12, 1974.
*
Since each reset level is set at a different voltage because of reset/kTC noise, described in Section 3.2, the varia-
tion is emphasized in the figure.
