Image Processing Reference
In-Depth Information
on
13
to realize a frame rate as high as 1.6 × 10
7
fps by using BSI for high sensitivity and
charge multiplication. However, it does have issues, such as increased load on cooling of
the system to suppress the rise in heat caused by high-frequency driving of a CCD, which
is a large capacitor.
7.3.1.4 Coexistence Type of Burst and Continuous Imaging Modes
A burst-type CMOS image sensor was also developed. By putting the CMOS sensor to
good use, analog frame memory areas are formed separate from the image area in the sen-
sor,
14
as shown in Figure 7.11 with 400(H) × 256(V) pixels.
On the top and bottom of the image area, a frame memory of 128 frames/pixel is formed
for temporary storage. Signals are read out from the image area to the memory at high
speed through 32 signal lines in each column, that is, four pixels per one output. The
sample and hold circuit of a CDS arranged as internal circuits in a pixel provide global
shutter function. Interestingly, it can capture both the burst imaging mode of 10
7
fps
(1 Tpixels/s) with 128 frames of 10
5
pixel numbers and the continuous imaging mode of
Horizontal scanning
and output circuits
20 parallels
Analog memory array
400(H) × 128(V) × 128 memories
Pixel array (image area)
400(H) × 256(V)
Analog memory array
400(H) × 128(V) × 128 memories
Horizontal scanning
and output circuits
20 parallels
FIGURE 7.11
Architecture of high-speed CMOS sensor. (Reprinted with permission from Tochigi, Y., Hanzawa, K., Kato, Y., Kuroda,
R., Mutoh, H., Hirose, R., Tominaga, H., Takubo, K., Kondo, Y., Sugawa, S.,
Proceedings of IEEE International Solid-State
Circuits Conference Digest of Technical Papers
, 22.2, pp. 382-384, San Francisco, CA, 2012.)
