Types of Image Sensors - Essential Principles of Image Sensors - page 109

The n -type region of the PD is connected to voltage source V dd , and the reset transistor
is formed between the p -type region of the PD and GND level. The p -type region is con-
nected to input of the first stage of an integrated four-stage CMOS inverter chain. The
voltage of the p -type region, which is at GND level just after reset operation, rises along
with an increase in signal charges (hole). When the voltage reaches the threshold voltage of
the first-stage inverter, the inverter output is inverted, which causes inverts of the follow-
ing inverters. The output of the final-stage inverter turns to high or “1” from low or “0.” It
makes reset transistor switch on-state to reset the p -type region of the PD to GND level.
Then, inverts of outputs of four inverters follow in series. Consequently, final-stage inverter
output is switched to low or “0,” which makes the reset transistor off-state to complete the
reset operation and the next signal charge integration starts. By a series of operations,
one pulse is output from the final stage of inverter chains. By using the PD capacitance
as one unit to measure charge quantity, one pulse is output and the PD is reset when a
predetermined charge quantity is integrated in the PD. Since higher-frequency clock pulse
is output for higher illumination, while the opposite situation occurs for darker areas, as
shown in Figure 5.65b, it can be considered that light intensity information is converted
to the frequency of output pulse. Only by counting the pulse number to code digitally is
pixel-level A/D conversion achieved. The reason a four-stage inverter chain is adopted is
to make time for the reset transistor to reset the operation with certainty by time delay of
the inverters.
In this sensor, quantized factors are space and amount of change of integrated charge
quantity in PD. So the signal output of the sensor is not integrated signal charge quantity S ,

VDD CMOS inverters

Photodiode

Pulse output

Reset
transistor

GND

(a)

High illumination

Darker area

(b) Time (5 ms/div)

FIGURE 5.65
Pulse output sensor: (a) pixel circuit diagram; (b) pulse output. (Reprinted with permission from Yang, W.,
Proceedings of the IEEE International Solid-State Circuits Conference, 41st ISSCC Digest of Technical Papers , 13.7,
pp. 230-231, San Francisco, CA, 1994.)