Image Processing Reference
In-Depth Information
RST
(reset
transistor)
TX
V
dd
Pixel
Drive
transistor
RS
(row select
transistor)
Load
transistor
V
LG
V
ss
FPN cancellation circuit (CDS)
CS
(column select
transistor)
Output
Horizontal access circuit
FIGURE 5.46
Schematic diagram of a 4-Tr pixel configuration CMOS sensor.
configuration. In readout operation, signal charges in the PD are transferred to FD by
applying readout pulse to TX, and potential change of FD is detected by the SFA, which is
made up of a drive transistor and load transistor as well as the 3-Tr pixel.
Figure 5.46 is a schematic diagram of a 4-Tr pixel configuration CMOS sensor. Overall,
the operation is the same as that of the 3-Tr sensor except for signal charge readout transfer
from PD to FD and reset operations caused by division of roles between PD and FD.
Figure 5.47 is a schematic diagram of the readout operation of one pixel in a 4-Tr pixel
CMOS sensor. Figure 5.47a and b show cross-sectional view and potential distribution in
operation, respectively. In Figure 5.47b, (1) shows just after exposure period completion
and signal charges
Q
sig
and noise charges
Q
noise
are integrated in the PD and FD, respec-
tively. At first, the SFA is activated by applying the row select pulse to row select transistor
RS and electrons start to flow from
V
ss
to
V
dd
, as shown in (2). Before readout operation,
noise charges
Q
noise
integrated in FD are reset also, as shown in (2). Then, the reset level of
FD is output as reset output voltage, as shown in (3). Signal charges
Q
sig
integrated in the
PD are transferred to FD by applying readout pulse generated by the vertical access circuit
to the gate of readout transfer transistor TX, as shown in (4). It should be noted that this is
the charge transfer operation mentioned in Section 5.1.2.2. The potential of FD is decrease
by the signal charge packet and the level is output as signal output voltage by SFA, as
shown in (5). After signal level is output, signal charges in FD are reset, as shown in (6).
Then one readout and output sequence is completed, as shown in (7). The next exposure
period starts when signal charge transfer is completed, as shown in (5).
The difference of signal output voltage and reset output voltage is obtained at the next
stage by an offset cancelation circuit. Because the reset situations of the FD of both of
them are the same, not only offset variation but also kTC noise of FD can be removed.
Because the time length between reset operation of FD and signal charge output is quite
short, the amount of integrated dark current at FD is negligible. Since no direct contact
