Hardware Reference
In-Depth Information
72 /*
73 * Kill the clock :
74 */
75 ugclk[PWMCLK_CNTL] = 0x5A000020; /* Kill clock */
76 pwm_ctl−>PWEN1 = 0; /* Disable PWM */
77 usleep(10);
78
79 /*
80 * Compute and set the divisor:
81 */
82 idiv = (long)( clock_rate / (double)freq );
83 if ( idiv < 1 ) {
84 idiv = 1; /* Lowest divisor */
85 rc = −1;
86 } else if ( idiv >= 0x1000 ) {
87 idiv = 0xFFF; /* Highest divisor */
88 rc = +1;
89 }
90
91 ugclk[PWMCLK_DIV] = 0x5A000000 | ( idiv << 12 );
92
93 /*
94 * Set source to oscillator and enable clock :
95 */
96 ugclk[PWMCLK_CNTL] = 0x5A000011;
97
98 /*
99 * GPIO 18 is PWM, when set to Alt Func 5 :
100 */
101 INP_GPIO(18); /* Set ALT = 0 */
102 SET_GPIO_ALT(18,5); /* Or in '5 ' */
103
104 pwm_ctl−>MODE1 = 0; /* PWM mode */
105 pwm_ctl−>RPTL1 = 0;
106 pwm_ctl−>SBIT1 = 0;
107 pwm_ctl−>POLA1 = 0;
108 pwm_ctl−>USEF1 = 0;
109 pwm_ctl−>MSEN1 = 0; /* PWM mode */
110 pwm_ctl−>CLRF1 = 1;
111 return rc ;
112 }
113
114 /*
115 * Initialize GPIO/PWM/CLK Access
116 */
