Hardware Reference
In-Depth Information
25 #define PWMCLK_CNTL 40
26 #define PWMCLK_DIV 41
27
28 static volatile unsigned *ugpio = 0;
29 static volatile unsigned *ugpwm = 0;
30 static volatile unsigned *ugclk = 0;
31
32 statics struct S_PWM_CTL {
33 unsigned PWEN1 : 1;
34 unsigned MODE1 : 1;
35 unsigned RPTL1 : 1;
36 unsigned SBIT1 : 1;
37 unsigned POLA1 : 1;
38 unsigned USEF1 : 1;
39 unsigned CLRF1 : 1;
40 unsigned MSEN1 : 1;
41 } volatile *pwm_ctl = 0;
42
43 static struct S_PWM_STA {
44 unsigned FULL1 : 1;
45 unsigned EMPT1 : 1;
46 unsigned WERR1 : 1;
47 unsigned RERR1 : 1;
48 unsigned GAP01 : 1;
49 unsigned GAP02 : 1;
50 unsigned GAP03 : 1;
51 unsigned GAP04 : 1;
52 unsigned BERR : 1;
53 unsigned STA1 : 1;
54 } volatile *pwm_sta = 0;
55
56 static volatile unsigned *pwm_rng1 = 0;
57 static volatile unsigned *pwm_dat1 = 0;
58
59 #define INP_GPIO(g) *( ugpio+((g )/10)) &=
~
(7<<(((g)%10)*3))
60 #define SET_GPIO_ALT(g,a) \
61 *(ugpio+(((g)/10))) |= (((a)<=3?(a)+4:((a)==4?3:2))<<(((g)%10)*3))
62
63 /*
64 * Establish the PWM frequency :
65 */
66 static int
67 pwm_frequency(float freq) {
68 const double clock_rate = 19200000.0;
69 long idiv;
70 int rc = 0;
71
