Environmental Engineering Reference
In-Depth Information
Gap-IMECA-Oriented Assessment of
FPGA-Based I&C Systems
discrepancies can be caused by design faults,
developer's errors, and/or errors in appropriate
procedures intended for the developer. Moreover,
during the subsequent stages of the overall devel-
opment process, existing problems in the product
can be either eliminated or multiplied. Then, it is
possible to represent the identified set of the
process' discrepancies (or single gap) in a form
of IMECA-based table, where each row corre-
sponds to a discrepancy within the process.
Such a complex gap can be eliminated, for
example, via the implementation of another devel-
opment process (see Figure 13b), which includes
As an illustrative example for the proposed ap-
proach, consider a typical development process
for a VHDL code, implemented by a developer
(see Figure 13a) of FPGA-based safety important
I&C system.
The input to the process is represented by a
technical specification document (containing the
comprehensive description of the object being
developed), and the result is the VHDL code
(development object). In such a case the possible
Figure 13. Development processes for VHDL code
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