Environmental Engineering Reference
In-Depth Information
important system attributes hierarchical model
consisting of i levels.
One of the possible ways to reveal criticality
of two-way influence for safety important system's
attributes is in creating of attributes influence
matrix. Such a problem can be solved, in particu-
lar, in the following ways:
A set of such “local” influence matrixes rep-
resents the case of a metric mostly intended for
independent assessment of the safety important
system's attributes within the single level.
2. Create the single “global” influence ma-
trix where each of all the n attributes (see
Equation(1)) is reflected by a single row and
appropriate column (see Figure 5).
1. Create a set of n “local” influence matrixes
for i hierarchical levels; each of the matrixes
consists of k i attributes (see Figure 4), and,
therefore of k i rows. Such number n can be
calculated using the following equation:
“Global” influence matrix can be considered
as another metric, which is suitable for assessment
of the safety important system as a whole.
Thus, on the one hand, such metrics allow shar-
ing SCS resources in order to assure the required
level of security (a vertical related to different
levels in Figure 3), on the other hand, they allow
optimizing the use of the resources (within the
same level, see Figure 3).
1
i
1
n
=
k x
(1)
x
=
The number of rows in each matrix associated
with the level m , where m =[1, i -1], is equal to a
number of attributes ( k m ) at the lower level m +1:
for example, the local matrix for a single attribute
of i -1 level consists of k i rows.
Cyber Security Threats and
Vulnerabilities for FPGA-
Based I&C Systems
At the present time, there is limited number of
potentially probable modes of cyber attacks on
FPGA technology, a list of which, along with their
short description, harmonized with Badrignans B.
et al., (Badrignans, B. et al., 2011), is given below.
Figure 4. Local influence matrix
1. Black Box Attack: An adversary inputs all
possible combinations to FPGA chip and
registers output states. Such an approach
provides potential possibility of reverse
engineering for FPGA electronic design,
integrated into a chip. In practice this ap-
proach is extremely hard to implement for
systems with complex logic.
2. Read-Back Attack: The attack is based on
a potential possibility of reading FPGA chip
configuration, usually, via JTAG interface
used in most FPGAs for debugging. Recently,
FPGA vendors have improved protection
measures to access chip configuration (for
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