Electric Clock for NanoMagnet Logic Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 91

Table 3. NML total power comparison with different clock systems.

Energy (fJ)
I Magnetic field 62
II STT-current 11
III Multiferroic 0.004
IV Magnetoelastic without compensation 0.052
V Magnetoelastic with compensation

0.006

VI CMOS LOP 21 nm 0.110

VII Adiabatic CMOS LOP 21 nm 0.040

Increasing the thickness of the piezoelectric layer generally improves the mate-
rial piezoelectric properties and simplifies the fabrication process at the cost of
improved energy consumption.
Finally a comparison between different NML clock solutions and CMOS tech-
nology is presented in Table 3 , comparing the total energy consumption of a
NAND gate. In case of magnetic field clock (I in Table 3 ) an adiabatic switch-
ing is considered, therefore the intrinsic energy consumption of each magnet is
assumed equal to 30 K b T . Clock wires are made of copper and have a section of
400 400 nm 2 , with a length of 200 nm. The current value used is extrapolated

from the experimental data shown in [ 11 ] and is assumed equal to 2 mA. With
these values the total energy consumption is 62 fJ. For the STT-current clock
(II in Table 3 ) the energy consumption is assumed equal to 1.6 fJ for each mag-
net [ 28 ], for a total of 11 fJ. In case of a pure multiferroic logic (III in Table 3 ),
data shown in [ 30 ] assume a power consumption of 0.004 fJ for a NAND gate.
With the clock solution here proposed the energy consumption in case of a 3

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3
terfenol NAND gate is equal to 0.052 fJ (IV in Table 3 ). This value is orders of
magnitude better than current-based clock systems. A comparison with a pure
multiferroic approach is not possible because the data reported in [ 30 ]donot
take into account the energy loss in the clock generation network. A compar-
ison among the different clock solutions applied to a complex circuit is shown
in [ 49 ], where a NML circuit for biosequences analysis [ 50 , 51 ] is presented. The
advantage of this clock solution in terms of power consumption is plain.
An important fact must be highlighted. From a circuital point of view every
mechanically isolated island is equivalent to a capacitor. As a consequence it is
possible to set up an appropriate RLC resonant circuit to recover the energy used
to charge the capacitance, reducing the NAND gate energy consumption from
0.052 fJ to 0.006 fJ (V in Table 3 ). Due to the presence of a parasitic resistance
it is not possible to completely recover the energy, nonetheless it is still possible
to obtain a good energy consumption reduction. This is particularly important
if higher thickness values must be used for the PZT substrate to improve the
piezoelectric properties. With higher thickness values the energy consumption
is bigger, but it can be compensated by recovering it with setting up a RLC
resonator. Considering instead a CMOS NAND gate (VI in Table 3 ) data extrap-
olated from ITRS roadmap indicates an energy consumption of 0.110 fJ for the

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